Circuits and Techniques for All-Digital Frequency Synthesizers and Design Automation

Abstract

As semiconductor fabrication process become complex to achieve target yield and performance in sub-20nm field-effect transistors (FETs), not only the number of design rule constraints (DRCs) exploded, but also the dependencies between different rules increased, which made manual layout design of custom chip more challenging and time consuming. While digital circuit design has been highly automated thanks to its better immunity to layout parasitic and mismatches, analog circuit design automation lags due to its layout sensitivity. As a solution for analog design automation, using standard digital flow to build a cell-based architecture has been suggested as one of few possibilities. This approach simplifies the design parameters to number of series/parallel cells from conventional width/lengths of every transistor, simplifying the modeling process. Also, it takes advantage of existing layout design engines that can handle complex DRCs, reducing one big step of design automation. Among analog circuits, clock generators have been extensively explored in the area of cell-based architecture due to the digital nature of clock signal and early development of all-digital architectures. But prior arts showed limits in two areas: 1) fully automating the design process starting from a user given specification, 2) systematic solution to alleviate the degradation of analog performance due to the automatic routing. In this dissertation, we propose an automated design flow for all digital phase locked loops (ADPLL) and architectural improvements including digital calibration scheme to push the performance limits of synthesizable clock generators. In chapter 2, design automation flow for baseline ADPLL architecture and novel feedforward scheme that doesn’t require gain calibration is proposed. By combining physics-based equation and simulation results, we show a sample efficient (3 sets of simulation required) modeling method that successfully predicts key metrics of digitally controlled ring oscillator (DCO) with error rate less than 1.5%. A prototype design was fabricated in 65nm process using the automation flow. We also propose a feedforward technique that selects the closest edge to the reference clock among interpolated DCO edges. This technique is amenable to PnR tool and reduces the jitter by 4.22x when the DCO noise dominates the TDC quantization noise. Chapter 3 analyzes PLL fractional spur’s impact on Bluetooth low energy (BLE) spectrum to define spectral mask for PLL that can satisfy that of the BLE. Also, we propose a novel two-step TDC architecture and calibration scheme to overcome the performance limits coming from random routings. The 1.8-2.7 GHz PLL was fabricated in 12nm FinFET technology, consuming 3.91 mW at 2.4006GHz achieving FoM of -220.7dB in fractional-N operation. Finally, chapter 4 proposes an all-digital fractional-N multiplying delay locked loop (MDLL) that uses reference triggered ring oscillator (RTRO) as a coarse DTC that reduces fine DTC range by 9x. Prototype design was fabricated in 65nm CMOS process and measured integer-N result shows 325 fs jitter and 16.1mW power consumption, achieving FoM of -237.7 dB. Simulated fractional-N operation shows worst case fractional spur of -41.9 dBc and rms jitter of 507 fs.