Overcoming the Limitations of Si-CMOS and Von Neuman Architectures by Adopting Beyond-Si Devices and Near-Memory Computation

Abstract

The advancement of Silicon CMOS technology has led to information technology innovation for decades. Transistor density, computation frequency, and storage capacity have been increased by several orders of magnitude, contributing to the thriving of artificial intelligence, cloud computing, the Internet of Things (IoT), etc. Those applications are in the trend of explosive progress, thus requiring continuous advancement in Si CMOS technology. However, current Si CMOS technology is confronting several challenges. First, scaling transistors down according to Moore’s law almost reaches its limitations. The memory-wall problem in Von Neumann architecture is also worsening due to the growing performance disparity between processors and memory, as well as the emergence of memory-intensive applications. Second, the increasing need for computing necessitates the application of digital technologies in extreme environments and conditions where Si CMOS is not functional. To tackle these limitations and lead further innovations, this dissertation explores the utilization of emerging beyond-Si devices and near-memory computing to address the limitations of Si CMOS technology and Von Neumann Architecture. First, this thesis introduces Silicon Carbide (SiC) processors for extremely high-temperature Venus surface exploration. The assessment indicates that the RISC-V-based SiC processors have an average throughput of 16.6× lower than the RAD6000 Si processors used in the earlier Mars Spirit and Opportunity rovers. If the proposed SiC processors are employed in the Venus lander, it is projected to move at a speed of 0.6 meters per hour and require 50 minutes for visual odometry processing. To provide guidance for enhancing the SiC processors’ performance, this study conducts a design space exploration of various factors, such as core complexity, core counts, cache capacity, and customization of instruction sets. Second, this thesis describes RecPIM: a PIM-enabled DRAM-RRAM hybrid memory system for accelerating deep learning recommendation models. RecPIM surpasses the CPU and PIM-only baselines by 2.6× and 4.8×, respectively. Compared to the CPU baseline, RecPIM conserves 1.7× more energy and enhances the energy-delay product (EDP) by 4.4×, on average. RecPIM incorporates wear-leveling techniques to achieve a practical lifespan of more than 12 years. Lastly, this thesis introduces a novel approach to accelerating the scalable de novo genome assembly process through Near-Memory Processing (NMP). This method adapts the PaKman algorithm, originally designed for distributed memory system, for efficient use in a single-node environment. It integrates an NMP system with several strategic optimizations to address the challenges associated with the complexity and computational demands of the large-scale de Bruijn graph (DBG) assembly. The proposed NMP system markedly reduces resource demands, enabling it to run on a lower-end server with hundreds of GBs of memory. This is a notable improvement compared to the original PaKman algorithm, which was run on a system with 1000 nodes and a total of 128 TB memory. Moreover, the NMP system achieves a performance gain of 3.07× compared to the CPU baseline. By enhancing the accessibility and cost-effectiveness of de novo genome assembly, this work facilitates rapid and efficient assembly for researchers.