Digital Signals Processing Techniques and ASIC Development for 3D CdZnTe Gamma-Ray Detectors

Abstract

Over the last 30 years, CdZnTe (CZT) radiation detectors have been developed into one competitive room-temperature option for gamma-ray spectroscopy and imaging. Electronic readout from triggered anode pixels and a single planar cathode enables the position of each interaction to be located with a resolution of < 500 um in all three dimensions at 662 keV. Using the 3D position of interaction as a basis for energy calibration, energy resolution of < 1% for all events, and best energy resolutions of < 0.35% resolution for single-pixel events at 662 keV have been demonstrated. The unique capabilities of 3D-CZT lend to its use in medical applications such as positron emission tomography (PET). One component of this work is the evaluation of the timing resolution achievable by 3D-CZT, a critical parameter for coincidence systems employed in PET imaging. Prior studies achieved timing resolutions of <10 ns using 1 cm thick CZT with GHz sampling systems and waveform fitting techniques. In this study, hand-held systems employing 1.5 cm thick CZT, sampling frequencies up to 80 MHz, and linear-fit-based digital signals processing (DSP) techniques yield a best timing resolution of 36.3 ns. Simulations based on the system response waveforms and measured system noise indicate that the measured timing resolution is in agreement with the limits imposed by cathode noise. Towards further optimization of timing resolution in 3D-CZT coincidence systems, investigations on the correlation between cathode noise and detector thickness, area, and applied bias are recommended.

System compactness is at a premium for any fields requiring portability such as military, space, and reactor inspection. For current 3D-CZT electronic readout, a CPU is required to perform complex filtering operations on the anode and cathode waveforms. Discrete analog-to-digital converters (ADCs), and a field programmable gate array (FPGA) are required to read out waveforms from the front-end electronics. To significantly reduce power consumption and area requirements, an application specific integrated circuit (ASIC) is proposed which brings the ADC, data acquisition (DAQ), and DSP all onto one piece of silicon. Four revisions of the DSP-DAQ-ADC ASIC have been taped out over the last four years on the TSMC 65nm MS RF GP technology. The 4th iteration of the chip is the first back-end digital ASIC used with 3D-CZT to demonstrate a calibrated energy spectrum, achieving a resolution of 0.6% for single-pixel events at 662 keV. With a die area of 3 mm x 3 mm and a total power consumption of 35 mW, the DSP-DAQ-ADCv4 ASIC is a step towards the next generation of low power, hand-held 3D-CZT systems.