Substrate response of a floating gate n-channel MOS memory cell subject to a positive linear ramp voltage

Abstract

A computer simulated substrate response of an n-channel MOS floating gate transistor to a positive linear ramping gate voltage was investigated. Device parameters, such as the channel length, effective electron mobility, substrate doping level and the gate voltage ramping rate were changed to see their effects on the substrate response. The substrate response was monitored by using the response of the surface potential at the mid-channel point. In the one-dimensional analysis it was found that the surface potential at the mid-channel point increased initially and dropped quickly after passing through its peak value and then decreased slowly. The mid-channel surface potential reached a higher peak value if the device had (1) a longer channel length, (2) a lower effective electron mobility, (3) a higher gate voltage ramping rate, or (4) a lower substrate doping level. Solutions show that the conditions for the mid-channel point to reach its peak surface potential faster are: (a) a shorter channel length, (b) a higher effective electron mobility, (c) a higher gate voltage ramping rate, and (d) a lower substrate doping level.