Hierarchical gate-array routing on a hypercube multiprocessor
dc.contributor.author | Olukotun, O. A. | en_US |
dc.contributor.author | Mudge, Trevor N. | en_US |
dc.date.accessioned | 2006-04-10T13:47:12Z | |
dc.date.available | 2006-04-10T13:47:12Z | |
dc.date.issued | 1990-04 | en_US |
dc.identifier.citation | Olukotun, O. A., Mudge, T. N. (1990/04)."Hierarchical gate-array routing on a hypercube multiprocessor." Journal of Parallel and Distributed Computing 8(4): 313-324. <http://hdl.handle.net/2027.42/28650> | en_US |
dc.identifier.uri | http://www.sciencedirect.com/science/article/B6WKJ-4CBVMKX-10/2/12781f5f5e39f8a07f42df0a404c6cc1 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/28650 | |
dc.description.abstract | Gate-arrays are the most common design style for semicustom VLSI integrated circuits. An important part of the gate-array design process is the routing of wires between the logic elements, which is an extremely compute-intensive operation. This paper presents an algorithm for routing gate-arrays that uses a hypercube connected parallel processor to provide the necessary computation power. In order to make optimal use of the hypercube, the routing algorithm is organized so that interprocessor communication is kept to minimum. It occurs only during the global routing and crossing placement phases of the algorithm, which constitute less than 15% of the total running time of the algorithm. On the basis of the results of executing the algorithm on two gate-array benchmarks the case is made for using hypercube multiprocessors as accelerators for compute-intensive CAD operations. | en_US |
dc.format.extent | 1421425 bytes | |
dc.format.extent | 3118 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | text/plain | |
dc.language.iso | en_US | |
dc.publisher | Elsevier | en_US |
dc.title | Hierarchical gate-array routing on a hypercube multiprocessor | en_US |
dc.type | Article | en_US |
dc.rights.robots | IndexNoFollow | en_US |
dc.subject.hlbsecondlevel | Philosophy | en_US |
dc.subject.hlbsecondlevel | Computer Science | en_US |
dc.subject.hlbtoplevel | Humanities | en_US |
dc.subject.hlbtoplevel | Engineering | en_US |
dc.description.peerreviewed | Peer Reviewed | en_US |
dc.contributor.affiliationum | Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109, USA | en_US |
dc.contributor.affiliationum | Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109, USA | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/28650/1/0000466.pdf | en_US |
dc.identifier.doi | http://dx.doi.org/10.1016/0743-7315(90)90130-H | en_US |
dc.identifier.source | Journal of Parallel and Distributed Computing | en_US |
dc.owningcollname | Interdisciplinary and Peer-Reviewed |
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