A hierarchical test generation methodology for digital circuits
dc.contributor.author | Bhattacharya, Debashis | en_US |
dc.contributor.author | Hayes, John P. (John Patrick) | en_US |
dc.date.accessioned | 2006-09-08T20:57:57Z | |
dc.date.available | 2006-09-08T20:57:57Z | |
dc.date.issued | 1990-05 | en_US |
dc.identifier.citation | Bhattacharya, Debashis; Hayes, John P.; (1990). "A hierarchical test generation methodology for digital circuits." Journal of Electronic Testing 1(2): 103-123. <http://hdl.handle.net/2027.42/43007> | en_US |
dc.identifier.issn | 0923-8174 | en_US |
dc.identifier.issn | 1573-0727 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/43007 | |
dc.description.abstract | A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach. | en_US |
dc.format.extent | 1507411 bytes | |
dc.format.extent | 3115 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | text/plain | |
dc.language.iso | en_US | |
dc.publisher | Kluwer Academic Publishers; Springer Science+Business Media | en_US |
dc.subject.other | Engineering | en_US |
dc.subject.other | Computer-Aided Engineering (CAD, CAE) and Design | en_US |
dc.subject.other | Electronic and Computer Engineering | en_US |
dc.subject.other | Digital Circuits | en_US |
dc.subject.other | Fault Modeling | en_US |
dc.subject.other | Hierarchical Testing | en_US |
dc.subject.other | High-level Circuit Models | en_US |
dc.subject.other | Test Generation | en_US |
dc.title | A hierarchical test generation methodology for digital circuits | en_US |
dc.type | Article | en_US |
dc.subject.hlbsecondlevel | Electrical Engineering | en_US |
dc.subject.hlbtoplevel | Engineering | en_US |
dc.description.peerreviewed | Peer Reviewed | en_US |
dc.contributor.affiliationum | Department of Electrical Engineering and Computer Science, The University of Michigan, 48109, Ann Arbor, MI, USA | en_US |
dc.contributor.affiliationother | Department of Electrical Engineering, Yale University, 06520, New Haven, CT, USA | en_US |
dc.contributor.affiliationumcampus | Ann Arbor | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/43007/1/10836_2004_Article_BF00137388.pdf | en_US |
dc.identifier.doi | http://dx.doi.org/10.1007/BF00137388 | en_US |
dc.identifier.source | Journal of Electronic Testing | en_US |
dc.owningcollname | Interdisciplinary and Peer-Reviewed |
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