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Testability Properties of Divergent Trees

dc.contributor.authorBlanton, R. D. (Shawn)en_US
dc.contributor.authorHayes, John P. (John Patrick)en_US
dc.date.accessioned2006-09-08T20:58:05Z
dc.date.available2006-09-08T20:58:05Z
dc.date.issued1997-12en_US
dc.identifier.citationBlanton, R.D. (Shawn); Hayes, John P.; (1997). "Testability Properties of Divergent Trees." Journal of Electronic Testing 11(3): 197-209. <http://hdl.handle.net/2027.42/43009>en_US
dc.identifier.issn0923-8174en_US
dc.identifier.issn1573-0727en_US
dc.identifier.urihttps://hdl.handle.net/2027.42/43009
dc.description.abstractThe testability of a class of regular circuits calleddivergent trees is investigated under a functional fault model. Divergent trees include such practical circuits as decoders anddemultiplexers. We prove that uncontrolled divergent trees aretestable with a fixed number of test patterns (C-testable) if andonly if the module function is surjective. Testable controlled treesare also surjective but require sensitizing vectors for errorpropagation. We derive the conditions for testing controlleddivergent trees with a test set whose size is proportional to thenumber of levels p found in the tree (L-testability). By viewing a tree as overlapping arrays of various types, we also deriveconditions for a controlled divergent tree to be C-testable. Typicaldecoders/demultiplexers are shown to only partially satisfy L- andC-testability conditions but a design modification that ensuresL-testability is demonstrated.en_US
dc.format.extent167961 bytes
dc.format.extent3115 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypetext/plain
dc.language.isoen_US
dc.publisherKluwer Academic Publishers; Springer Science+Business Mediaen_US
dc.subject.otherEngineeringen_US
dc.subject.otherComputer-Aided Engineering (CAD, CAE) and Designen_US
dc.subject.otherElectronic and Computer Engineeringen_US
dc.subject.otherFault Detectionen_US
dc.subject.otherFault Modelingen_US
dc.subject.otherRegular Circuitsen_US
dc.subject.otherInteractive Logic Arraysen_US
dc.subject.otherStructured Circuitsen_US
dc.subject.otherTest Generationen_US
dc.titleTestability Properties of Divergent Treesen_US
dc.typeArticleen_US
dc.subject.hlbsecondlevelElectrical Engineeringen_US
dc.subject.hlbtoplevelEngineeringen_US
dc.description.peerreviewedPeer Revieweden_US
dc.contributor.affiliationumAdvanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, MI 48109-2122en_US
dc.contributor.affiliationotherCenter for Electronic Design Automation, ECE Department, Carnegie Mellon University, Pittsburgh, PA, 15213-3890en_US
dc.contributor.affiliationumcampusAnn Arboren_US
dc.description.bitstreamurlhttp://deepblue.lib.umich.edu/bitstream/2027.42/43009/1/10836_2004_Article_146935.pdfen_US
dc.identifier.doihttp://dx.doi.org/10.1023/A:1008262321471en_US
dc.identifier.sourceJournal of Electronic Testingen_US
dc.owningcollnameInterdisciplinary and Peer-Reviewed


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