Testability Properties of Divergent Trees
dc.contributor.author | Blanton, R. D. (Shawn) | en_US |
dc.contributor.author | Hayes, John P. (John Patrick) | en_US |
dc.date.accessioned | 2006-09-08T20:58:05Z | |
dc.date.available | 2006-09-08T20:58:05Z | |
dc.date.issued | 1997-12 | en_US |
dc.identifier.citation | Blanton, R.D. (Shawn); Hayes, John P.; (1997). "Testability Properties of Divergent Trees." Journal of Electronic Testing 11(3): 197-209. <http://hdl.handle.net/2027.42/43009> | en_US |
dc.identifier.issn | 0923-8174 | en_US |
dc.identifier.issn | 1573-0727 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/43009 | |
dc.description.abstract | The testability of a class of regular circuits calleddivergent trees is investigated under a functional fault model. Divergent trees include such practical circuits as decoders anddemultiplexers. We prove that uncontrolled divergent trees aretestable with a fixed number of test patterns (C-testable) if andonly if the module function is surjective. Testable controlled treesare also surjective but require sensitizing vectors for errorpropagation. We derive the conditions for testing controlleddivergent trees with a test set whose size is proportional to thenumber of levels p found in the tree (L-testability). By viewing a tree as overlapping arrays of various types, we also deriveconditions for a controlled divergent tree to be C-testable. Typicaldecoders/demultiplexers are shown to only partially satisfy L- andC-testability conditions but a design modification that ensuresL-testability is demonstrated. | en_US |
dc.format.extent | 167961 bytes | |
dc.format.extent | 3115 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | text/plain | |
dc.language.iso | en_US | |
dc.publisher | Kluwer Academic Publishers; Springer Science+Business Media | en_US |
dc.subject.other | Engineering | en_US |
dc.subject.other | Computer-Aided Engineering (CAD, CAE) and Design | en_US |
dc.subject.other | Electronic and Computer Engineering | en_US |
dc.subject.other | Fault Detection | en_US |
dc.subject.other | Fault Modeling | en_US |
dc.subject.other | Regular Circuits | en_US |
dc.subject.other | Interactive Logic Arrays | en_US |
dc.subject.other | Structured Circuits | en_US |
dc.subject.other | Test Generation | en_US |
dc.title | Testability Properties of Divergent Trees | en_US |
dc.type | Article | en_US |
dc.subject.hlbsecondlevel | Electrical Engineering | en_US |
dc.subject.hlbtoplevel | Engineering | en_US |
dc.description.peerreviewed | Peer Reviewed | en_US |
dc.contributor.affiliationum | Advanced Computer Architecture Laboratory, EECS Department, University of Michigan, Ann Arbor, MI 48109-2122 | en_US |
dc.contributor.affiliationother | Center for Electronic Design Automation, ECE Department, Carnegie Mellon University, Pittsburgh, PA, 15213-3890 | en_US |
dc.contributor.affiliationumcampus | Ann Arbor | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/43009/1/10836_2004_Article_146935.pdf | en_US |
dc.identifier.doi | http://dx.doi.org/10.1023/A:1008262321471 | en_US |
dc.identifier.source | Journal of Electronic Testing | en_US |
dc.owningcollname | Interdisciplinary and Peer-Reviewed |
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