Scalable Test Generators for High-Speed Datapath Circuits
dc.contributor.author | Al-Asaad, Hussain | en_US |
dc.contributor.author | Hayes, John P. (John Patrick) | en_US |
dc.contributor.author | Murray, Brian T. | en_US |
dc.date.accessioned | 2006-09-08T20:58:09Z | |
dc.date.available | 2006-09-08T20:58:09Z | |
dc.date.issued | 1998-02 | en_US |
dc.identifier.citation | Al-Asaad, Hussain; Hayes, John P.; Murray, Brian T.; (1998). "Scalable Test Generators for High-Speed Datapath Circuits." Journal of Electronic Testing 12 (1-2): 111-125. <http://hdl.handle.net/2027.42/43010> | en_US |
dc.identifier.issn | 0923-8174 | en_US |
dc.identifier.issn | 1573-0727 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/43010 | |
dc.description.abstract | This paper explores the design of efficient test sets and test-pattern generators for on-line BIST. The target applications are high-performance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carry-lookahead, most existing BIST methods are unsuitable for these applications. High-level models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carry-lookahead adder, an arithmetic-logic unit, and a multiplier-adder. | en_US |
dc.format.extent | 1316297 bytes | |
dc.format.extent | 3115 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | text/plain | |
dc.language.iso | en_US | |
dc.publisher | Kluwer Academic Publishers; Springer Science+Business Media | en_US |
dc.subject.other | Engineering | en_US |
dc.subject.other | Computer-Aided Engineering (CAD, CAE) and Design | en_US |
dc.subject.other | Electronic and Computer Engineering | en_US |
dc.subject.other | Built-in Self-test | en_US |
dc.subject.other | Carry Lookahead | en_US |
dc.subject.other | Datapath Circuits | en_US |
dc.subject.other | On-line Testing | en_US |
dc.subject.other | Scalability | en_US |
dc.subject.other | Test Generation | en_US |
dc.title | Scalable Test Generators for High-Speed Datapath Circuits | en_US |
dc.type | Article | en_US |
dc.subject.hlbsecondlevel | Electrical Engineering | en_US |
dc.subject.hlbtoplevel | Engineering | en_US |
dc.description.peerreviewed | Peer Reviewed | en_US |
dc.contributor.affiliationum | Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, 1301 Beal Avenue, Ann Arbor, MI, 48109-2122 | en_US |
dc.contributor.affiliationum | Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, 1301 Beal Avenue, Ann Arbor, MI, 48109-2122 | en_US |
dc.contributor.affiliationother | Electrical and Electronics Department, General Motors R&D Center, 30500 Mound Road, Warren, MI, 48090-9055 | en_US |
dc.contributor.affiliationumcampus | Ann Arbor | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/43010/1/10836_2004_Article_154697.pdf | en_US |
dc.identifier.doi | http://dx.doi.org/10.1023/A:1008242108853 | en_US |
dc.identifier.source | Journal of Electronic Testing | en_US |
dc.owningcollname | Interdisciplinary and Peer-Reviewed |
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