The Coupling Model for Function and Delay Faults
dc.contributor.author | Yi, Joonhwan | en_US |
dc.contributor.author | Hayes, John P. (John Patrick) | en_US |
dc.date.accessioned | 2006-09-08T20:58:17Z | |
dc.date.available | 2006-09-08T20:58:17Z | |
dc.date.issued | 2005-12 | en_US |
dc.identifier.citation | Yi, Joonhwan; Hayes, John P.; (2005). "The Coupling Model for Function and Delay Faults." Journal of Electronic Testing 21(6): 631-649. <http://hdl.handle.net/2027.42/43012> | en_US |
dc.identifier.issn | 0923-8174 | en_US |
dc.identifier.issn | 1573-0727 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/43012 | |
dc.description.abstract | We propose a high-level fault model, the coupling fault (CF) model, that aims to cover both functional and timing faults in an integrated way. The basic properties of CFs and the corresponding tests are analyzed, focusing on their relationship with other fault models and their test requirements. A test generation program COTEGE for CFs is presented. Experiments with COTEGE are described which show that (reduced) coupling test sets can efficiently cover standard stuck-at-0/1 faults in a variety of different realizations. The corresponding coupling delay tests detect all robust path delay faults in any realization of a logic function. | en_US |
dc.format.extent | 2367781 bytes | |
dc.format.extent | 3115 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | text/plain | |
dc.language.iso | en_US | |
dc.publisher | Kluwer Academic Publishers; Springer Science + Business Media, Inc. | en_US |
dc.subject.other | Engineering | en_US |
dc.subject.other | Computer-Aided Engineering (CAD, CAE) and Design | en_US |
dc.subject.other | Electronic and Computer Engineering | en_US |
dc.subject.other | Circuits and Systems | en_US |
dc.subject.other | Delay Faults | en_US |
dc.subject.other | Fault Modeling | en_US |
dc.subject.other | Functional Faults | en_US |
dc.subject.other | Test Generation | en_US |
dc.title | The Coupling Model for Function and Delay Faults | en_US |
dc.type | Article | en_US |
dc.subject.hlbsecondlevel | Electrical Engineering | en_US |
dc.subject.hlbtoplevel | Engineering | en_US |
dc.description.peerreviewed | Peer Reviewed | en_US |
dc.contributor.affiliationum | Department of Electrical Engineering and Computer Science, University of Michigan, 1301 Beal Avenue, Ann Arbor, MI, 48109, USA | en_US |
dc.contributor.affiliationother | Telecommunication Research Center, Samsung Electronics Corporation, Suwon, Kyunggi-Do, Republic of Korea | en_US |
dc.contributor.affiliationumcampus | Ann Arbor | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/43012/1/10836_2005_Article_3476.pdf | en_US |
dc.identifier.doi | http://dx.doi.org/10.1007/s10836-005-3476-y | en_US |
dc.identifier.source | Journal of Electronic Testing | en_US |
dc.owningcollname | Interdisciplinary and Peer-Reviewed |
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