Cache coherence requirements for interprocess rendezvous
dc.contributor.author | Mudge, Trevor N. | en_US |
dc.date.accessioned | 2006-09-11T14:59:36Z | |
dc.date.available | 2006-09-11T14:59:36Z | |
dc.date.issued | 1990-02 | en_US |
dc.identifier.citation | Mudge, Trevor N.; (1990). "Cache coherence requirements for interprocess rendezvous." International Journal of Parallel Programming 19(1): 31-51. <http://hdl.handle.net/2027.42/44571> | en_US |
dc.identifier.issn | 0885-7458 | en_US |
dc.identifier.issn | 1573-7640 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/44571 | |
dc.description.abstract | Multiprocessors in which a shared bus is used by the processor to communicate with common memory are an emerging class of machines where there is a need to support parallel programming languages. A language construct that is found in a number of parallel programming languages to support synchronization and communication in the interprocess rendezvous. Shared-bus multiprocessor require a protocol to keep the date in their caches coherent. There are two major categories of these protocols: invalidation and write-boadcast. This paper examines the requirements for cache coherence protocols to support efficient interprocessor rendezvous. The approach taken is to examine the memory referencing patterns to the run-time data structures during rendezvous execution. The appropriate coherence protocol is shown to be a function of the processor scheduling strategy used by the run-time system at synchronzation points during the rendezvous. When processes migrate freely as a result of the scheduling strategy, invalidation protocols are found to be more efficient. When migration is restricted by the scheduler, write-broadcast protocols are more efficient. | en_US |
dc.format.extent | 1167493 bytes | |
dc.format.extent | 3115 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | text/plain | |
dc.language.iso | en_US | |
dc.publisher | Kluwer Academic Publishers-Plenum Publishers; Plenum Publishing Corporation ; Springer Science+Business Media | en_US |
dc.subject.other | Cache Coherence | en_US |
dc.subject.other | Software Engineering/Programming and Operating Systems | en_US |
dc.subject.other | Computer Science | en_US |
dc.subject.other | Concurrent Programming Languages | en_US |
dc.subject.other | Processor Architectures | en_US |
dc.subject.other | Theory of Computation | en_US |
dc.subject.other | Rendezvous | en_US |
dc.subject.other | Run-time Systems | en_US |
dc.subject.other | Process Migration | en_US |
dc.title | Cache coherence requirements for interprocess rendezvous | en_US |
dc.type | Article | en_US |
dc.subject.hlbsecondlevel | Philosophy | en_US |
dc.subject.hlbsecondlevel | Computer Science | en_US |
dc.subject.hlbtoplevel | Humanities | en_US |
dc.subject.hlbtoplevel | Engineering | en_US |
dc.description.peerreviewed | Peer Reviewed | en_US |
dc.contributor.affiliationum | Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, 48109-2122, Ann Arbor, Michigan | en_US |
dc.contributor.affiliationumcampus | Ann Arbor | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/44571/1/10766_2005_Article_BF01407863.pdf | en_US |
dc.identifier.doi | http://dx.doi.org/10.1007/BF01407863 | en_US |
dc.identifier.source | International Journal of Parallel Programming | en_US |
dc.owningcollname | Interdisciplinary and Peer-Reviewed |
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