Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors
dc.contributor.author | Hong, Inki | en_US |
dc.contributor.author | Potkonjak, Miodrag | en_US |
dc.contributor.author | Papaefthymiou, Marios | en_US |
dc.date.accessioned | 2006-09-11T15:17:43Z | |
dc.date.available | 2006-09-11T15:17:43Z | |
dc.date.issued | 1999-10 | en_US |
dc.identifier.citation | Hong, Inki; Potkonjak, Miodrag; Papaefthymiou, Marios; (1999). "Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors." Design Automation for Embedded Systems 4(4): 311-327. <http://hdl.handle.net/2027.42/44804> | en_US |
dc.identifier.issn | 0929-5585 | en_US |
dc.identifier.issn | 1572-8080 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/44804 | |
dc.description.abstract | Scheduling is one of the most often addressed optimization problems in DSP compilation, behavioral synthesis, and system-level synthesis research. With the rapid pace of changes in modern DSP applications requirements and implementation technologies, however, new types of scheduling challenges arise. This paper is concerned with the problem of scheduling blocks of computations in order to optimize the efficiency of their execution on programmable embedded systems under a realistic timing model of their processors. We describe an effective scheme for scheduling the blocks of any computation on a given system architecture and with a specified algorithm implementing each block. We also present algorithmic techniques for performing optimal block scheduling simultaneously with optimal architecture and algorithm selection. Our techniques address the block scheduling problem for both single- and multiple-processor system platforms and for a variety of optimization objectives including throughput, cost, and power dissipation. We demonstrate the practical effectiveness of our techniques on numerous designs and synthetic examples. | en_US |
dc.format.extent | 174847 bytes | |
dc.format.extent | 3115 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | text/plain | |
dc.language.iso | en_US | |
dc.publisher | Kluwer Academic Publishers; Springer Science+Business Media | en_US |
dc.subject.other | Engineering | en_US |
dc.subject.other | Special Purpose and Application-Based Systems | en_US |
dc.subject.other | Computer-Aided Engineering (CAD, CAE) and Design | en_US |
dc.subject.other | Electronic and Computer Engineering | en_US |
dc.subject.other | Circuits and Systems | en_US |
dc.subject.other | Block Scheduling | en_US |
dc.subject.other | Context Switching Minimization | en_US |
dc.subject.other | Architecture Selection | en_US |
dc.subject.other | Algorithm Selection | en_US |
dc.title | Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors | en_US |
dc.type | Article | en_US |
dc.subject.hlbsecondlevel | Computer Science | en_US |
dc.subject.hlbtoplevel | Engineering | en_US |
dc.description.peerreviewed | Peer Reviewed | en_US |
dc.contributor.affiliationum | EECS Department, University of Michigan, Ann Arbor | en_US |
dc.contributor.affiliationother | Computer Science Department, University of California, Los Angeles | en_US |
dc.contributor.affiliationother | Computer Science Department, University of California, Los Angeles | en_US |
dc.contributor.affiliationumcampus | Ann Arbor | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/44804/1/10617_2004_Article_239764.pdf | en_US |
dc.identifier.doi | http://dx.doi.org/10.1023/A:1008921705476 | en_US |
dc.identifier.source | Design Automation for Embedded Systems | en_US |
dc.owningcollname | Interdisciplinary and Peer-Reviewed |
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