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A fabrication process for integrating polysilicon microstructures with post-processed CMOS circuits

dc.contributor.authorGianchandani, Yogesh B.en_US
dc.contributor.authorKim, H.en_US
dc.contributor.authorShinn, M.en_US
dc.contributor.authorHa, B.en_US
dc.contributor.authorLee, B.en_US
dc.contributor.authorNajafi, Khalilen_US
dc.contributor.authorSong, C.en_US
dc.date.accessioned2006-12-19T19:08:23Z
dc.date.available2006-12-19T19:08:23Z
dc.date.issued2000-09-01en_US
dc.identifier.citationGianchandani, Y B; Kim, H; Shinn, M; Ha, B; Lee, B; Najafi, K; Song, C (2000). "A fabrication process for integrating polysilicon microstructures with post-processed CMOS circuits." Journal of Micromechanics and Microengineering. 10(3): 380-386. <http://hdl.handle.net/2027.42/49027>en_US
dc.identifier.issn0960-1317en_US
dc.identifier.urihttps://hdl.handle.net/2027.42/49027
dc.description.abstractA MEMS-first fabrication process for integrating CMOS circuits with polysilicon micromechanical structures is described in detail. The overall process uses 18 masks (22 lithography steps) to merge a p-well LOCOS CMOS process that has one metal and two polysilicon layers with a surface micromachining process that has three layers of polysilicon. The microstructures are formed within recesses on the surface of silicon wafers such that their uppermost surfaces are coplanar with the remainder of the substrate. No special planarization technique, such as chemical-mechanical polishing, is used in the work described here. Special aspects of the process include provisions to improve lithography within the recesses, to protect the microstructures during the circuit fabrication, and to implement an effective lead transfer between the microstructures and the on-chip circuitry. The process is validated using a test vehicle that includes accelerometers and gyroscopes interfaced with sensing circuits. Measured transistor parameters match those obtained in standard CMOS, with NMOS and PMOS thresholds at 0.76 V and -0.96 V, respectively.en_US
dc.format.extent3118 bytes
dc.format.extent377747 bytes
dc.format.mimetypetext/plain
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.publisherIOP Publishing Ltden_US
dc.titleA fabrication process for integrating polysilicon microstructures with post-processed CMOS circuitsen_US
dc.typeArticleen_US
dc.subject.hlbsecondlevelPhysicsen_US
dc.subject.hlbtoplevelScienceen_US
dc.description.peerreviewedPeer Revieweden_US
dc.contributor.affiliationumCenter for Integrated Microsystems, EECS Department, University of Michigan, Ann Arbor, MI 48109-2122, USAen_US
dc.contributor.affiliationotherDepartment of Electrical and Computer Engineering, University of Wisconsin, 1415 Engineering Drive, WI 53706-1691, USA;en_US
dc.contributor.affiliationotherSamsung Advanced Institute of Technology, Suwon, Koreaen_US
dc.contributor.affiliationotherSamsung Advanced Institute of Technology, Suwon, Koreaen_US
dc.contributor.affiliationotherSamsung Advanced Institute of Technology, Suwon, Koreaen_US
dc.contributor.affiliationotherSamsung Advanced Institute of Technology, Suwon, Koreaen_US
dc.contributor.affiliationotherSamsung Advanced Institute of Technology, Suwon, Koreaen_US
dc.contributor.affiliationumcampusAnn Arboren_US
dc.description.bitstreamurlhttp://deepblue.lib.umich.edu/bitstream/2027.42/49027/2/jm0312.pdfen_US
dc.identifier.doihttp://dx.doi.org/10.1088/0960-1317/10/3/312en_US
dc.identifier.sourceJournal of Micromechanics and Microengineering.en_US
dc.owningcollnameInterdisciplinary and Peer-Reviewed


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