Maskless Laser-Write Lithography of a-Si:H TFT Passive Pixel Sensor for Hemispherical Imager

Abstract

Current state-of the art image sensor technology has been developed on a flat surface. Recently, due to the unique advantages of a hemispherical image sensor, various methods have been proposed to implement optoelectronic devices on non-planar surfaces. However, more advanced strategy is necessary to realize active-matrix high resolution pixel array on non-planar surfaces. In this dissertation we demonstrate the fabrication of a-Si:H TFTs and passive pixel sensor (PPS) circuits on a curved glass substrate using maskless laser-write lithography (LWL). Further integration of solution-processable organic photodiodes with PPS circuit will realize imagers on a curved surface. First we introduce and discuss the electrical properties and instability of advanced a-Si:H TFT structures for pixel switch applications. Asymmetric electrical properties and the relationship between single and multiple hexagonal TFTs are also established. We used maskless laser-write lithography (LWL) system on a planar surface to demonstrate the feasibility of LWL in fabricating a-Si:H TFTs. We further develop necessary modifications of the LWL system for curved surface application. The fabricated a-Si:H TFTs with a channel length of 10 µm on a curved surface show acceptable electrical performance as a pixel switch. A high level-to-level alignment accuracy (< ± 2 µm) is achieved. The variations of electrical parameters over different curved locations are not significant. Extensive study of the a-Si:H TFTs threshold voltage shift (ΔVth) is conducted under prolonged bias-temperature stress condition. Metal interconnect lines over the transition between curved and flat surfaces of a single substrate is demonstrated, which is necessary for placing contact pads on the flat area. Finally we fabricated 128x128 a-Si:H TFT PPS array with 50 µm pixel pitch on a 4″ silicon wafer to be integrated with the organic photodiode for imager. The pixel circuit consists of fork-shaped a-Si:H TFT (W/L = 40/5) and a storage capacitor (CST, 0.1 pF).