Variability Aware Analysis and Optimization of VLSI Circuits.

Abstract

Continued scaling of semiconductor technology has greatly increased the complexity of the manufacturing process, and Design for Manufacturing (DFM) has emerged as an important topic of research over the last decade. DFM strives to reduce variability in Integrated Circuits through extensive modeling and analysis of process induced variability. This dissertation focuses on modeling, analysis and optimization techniques to manage variability within IC design. This dissertation begins with proposing the use of so called soft-edge flip-flops with a small window of transparency, instead of a hard edge for capturing data. Soft edge flip-flops allow time borrowing and averaging across stages, making the design less sensitive to process variations. Next four chapters model the layout dependence of mechanical stress and explore techniques to exploit the layout dependencies of mechanically stressed silicon through mechanical stress aware design and optimization. Chapter 3 uses mechanical stress aware standard cell library design in conjunction with dual threshold voltage (Vth) assignment to achieve optimal power-performance tradeoff, and decrease leakage power consumption by ~24%. Chapter 4 discusses a standard cell library design technique called STEEL. Chapter 5 presents compact closed-form models for layout dependence of process induced stress, and its impact on carrier mobility. Chapter 6 proposes a technique to model non-rectangular gates (NRG) with non-uniform carrier mobility to enable accurate prediction of both device drive current and leakage. Next chapter studies the impact of Rapid Thermal Anneal (RTA) temperature variation on circuit timing and leakage, and proposes techniques to minimize the impact of anneal temperature variation. Chapters 8 and 9 show significant impact of different Double Patterning Lithography (DPL) techniques on Static random-access memory (SRAM) robustness through measurement and simulation, and propose DPL-aware sizing optimization of SRAM cell. Experimental results based on 45nm industrial models show that using the best DPL option for each layer, along with the sizing optimization presented, can achieve single exposure robustness together with improved DPL printability at nearly no overhead. Finally, a framework that captures through-silicon via (TSV) induced mechanical stress and its impact on device mobility is discussed, and TSV stress is shown to cause delay variations of up to 6.9%.