A Cell-Based Design Methodology for Synthesizable RF/Analog Circuits.

Abstract

As CMOS processes scale and digital gates become faster, it is practical to implement precisely-timed digital circuits switching in the GHz range. As a result, traditionally analog circuits have moved towards mostly-digital designs, utilizing accurate time control and digital signal processing. Recently published all-digital architectures have shown several advantages over conventional analog circuits in terms of area, scalability, testability, and programmability. This thesis proposes a cell-based design methodology for synthesizable RF/analog circuits, where all functional blocks are not only implemented in all-digital architectures, but they are also described in a hardware description language, synthesized from commercial standard cell libraries, and automatically placed and routed using design tools. This cell-based design procedure significantly shortens the design time, and enhances portability of the circuits for various applications and different design nodes. A cell-based digitally controlled oscillator (DCO) is proposed as a core block for synthesizable circuits. The DCO consists of tri-state buffers from standard cell libraries, and the frequency of the DCO is digitally controlled by turning on/off the buffers. Instead of custom layout, the buffers in the DCO are automatically placed and routed (P&R), and systematic mismatch from automatic P&R is modeled and utilized to characterize the DCO in the design phase. Calibration schemes utilizing systematic mismatch are also proposed to achieve higher DCO resolution. This thesis presents an ultra-wideband (UWB) transmitter, a time-to-digital converter (TDC), and a PLL in 65nm CMOS technologies as prototypes of cell-based circuits. The UWB transmitters embed the proposed DCO to control the center frequency and width of output pulses in the 3.1GHz-5.0GHz UWB band, and the measured active energy efficiency of the transmitter ranges from 12pJ/pulse to 19pJ/pulse. The TDC adopts a cyclic Vernier structure, where two DCOs are oscillating with slightly different periods. The resolution of the TDC is the difference between two periods, which is measured as low as 8ps. The prototype PLL adopts the TDC and the DCO, and shows 3.2psrms of period jitter at 2.5GHz output frequency, which is comparable to state-of-the-art full-custom ADPLLs.