An Active Thin-Film Cochlear Electrode Array with Monolithic Backing and Curl.

Abstract

Cochlear implants for the deaf are the most successful neural prostheses; however, pitch perception remains relatively poor. The size of the scala tympani into which the electrode array is inserted limits the number of electrodes to about twenty-four using conventional wire-bundle arrays. Thin-film arrays can offer significant advantages by increasing the number of sites, reducing damage to residual hearing with smaller and more flexible arrays, and allowing deeper insertion (greater pitch range). This thesis creates an active cochlear array that builds on the success of a previous-generation Michigan array by increasing the reliability, usability and functionality. A robust and flexible 32-site prototype cochlear electrode array for a 128-site human array has been developed. Molded and thin-film backings for this array have been created for positioning the array inside the cochlea and close to the modiolar wall. The array has been integrated into the commercial molding process of Cochlear Ltd., as well as into a custom molding process created as part of this thesis. Batch-fabricated backings that include flexible parylene rings and self-curling parylene layers have also been created. These backings can achieve a minimum radius of curvature less than 0.5 mm. Array stiffness can be graded from 0.2 k·N/m2 to 1.4 k·N/m2 with parylene rings to increase the rigidity seven-fold over that of a flat parylene array. These parylene arrays have achieved full insertion into cat and guinea pig cochleae during in-vivo implants. The arrays have achieved the deepest insertions to date (more than 8mm in some cases). Flexible guinea pig arrays achieved atraumatic implantations with no visible damage to the scala media. A 32-site, 4-channel Application Specific Integrated Circuit (ASIC) was realized in 0.5μm technology to support a wide range of multisite multipolar stimulus configurations using a distributed Digital to Analog Converter (DAC) architecture. It fits within the space of the otic bulla having a size of 2.2 mm by 2.5 mm, and operates from a ±2.5 V supply at clock speeds up to 500 kHz. The maximum power consumption of the ASIC is 2.5 mW when outputting 500 μA and it is compatible with back voltages exceeding ±2V.