High‐performance top‐gate a‐Si:H TFTs for AMLCDs

Abstract

High‐performance top‐gate hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) structures have been fabricated over a large area from plasma‐enhanced chemical vapor deposition (PECVD) materials. The electrical performances of the top‐gate a‐Si:H TFT (μ FE ≅0.75cm 2 /Vsec, V T ≅3.5V, S ≅0.55V/dec) are comparable to the electrical performances observed for an inverted‐staggered bottom‐gate a‐Si:H TFT. We have shown that the TFT field‐effect mobility first increases with the a‐Si:H thickness, and then decreases for thicker a‐Si:H films. This change of the electrical performances can be associated either with the variation of a‐Si:H microstructure with film thickness during the PECVD processes or a large density of TFT back interface states; it also involves the source/drain parasitic access resistances, especially for thick a‐Si:H layers.