Applications of Semiconductor Nanowires for Nanoelectronics and Nanoelectromechanical Systems.
dc.contributor.author | Fung, Wayne Y. | en_US |
dc.date.accessioned | 2012-10-12T15:25:00Z | |
dc.date.available | NO_RESTRICTION | en_US |
dc.date.available | 2012-10-12T15:25:00Z | |
dc.date.issued | 2012 | en_US |
dc.date.submitted | 2012 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/93932 | |
dc.description.abstract | The tremendous success of complementary metal oxide semiconductor (CMOS) technology over the last five decades is now facing serious challenges due to aggressive device scaling. To this end, novel nanoscale materials including graphene, carbon nanotubes, and semiconductor nanowires have attracted much interest with the expectation that such materials may be able to complement or replace CMOS in the future. In particular, semiconductor nanowires (NWs) hold much technological promise. These are single-crystals with diameters of a few nanometers and lengths up to tens of micrometers, typically grown through a vapor-liquid-solid (VLS) process mediated by metal catalyst nanoparticles. Here we explore the technological potential of NWs along three fronts. First, we develop growth techniques for the growth of Si and Ge NWs with an eye toward hybrid nanowire-CMOS systems. We demonstrate the growth of Si NWs using CMOS-compatible Al as the catalyst, with high yield, small diameter, and recovery of semiconducting behavior at small diameter. We also develop the growth of vertical epitaxial Ge and Ge/Si core/shell NWs on Si, with diameter ~20 nm and at high nucleation and vertical yields. Second, using these vertical NWs, we investigate the prospects for a vertical Ge NW-based tunnel field-effect transistor (TFET). We fabricate vertical Esaki diodes using the heterojunction at the interface between the Ge NW and Si substrate. At room temperature a representative device shows a peak-to-valley current ratio of 2.75, a peak current density of 2.4 kA/cm^2, and a tunnel current density of 237 kA/cm^2 at 1 V reverse bias. The temperature dependent-behavior of the diodes suggest that this interface has a low defect density and thus would be suitable for TFET applications. Next we grow vertical epitaxial Ge NWs on Si nanopillars at sub-eutectic temperatures; this development will help create ultrasharp heterojunctions and enable optimized gate alignment for a vertical TFET. We also develop fabrication techniques for the construction of vertical FETs. Finally, we explore nanowire-based nanoelectromechanical systems (NEMS). We demonstrate a NEMS resonator consisting of a doubly clamped nanowire. Our devices feature high quality factor (Q ~ 2200), electrical actuation and detection, and selective actuation of different vibrational modes. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Nanoelectromechanical System | en_US |
dc.subject | Nanowire | en_US |
dc.subject | Field-effect Transistor | en_US |
dc.subject | Esaki Diode | en_US |
dc.subject | Germanium | en_US |
dc.subject | Silicon | en_US |
dc.title | Applications of Semiconductor Nanowires for Nanoelectronics and Nanoelectromechanical Systems. | en_US |
dc.type | Thesis | en_US |
dc.description.thesisdegreename | PhD | en_US |
dc.description.thesisdegreediscipline | Electrical Engineering | en_US |
dc.description.thesisdegreegrantor | University of Michigan, Horace H. Rackham School of Graduate Studies | en_US |
dc.contributor.committeemember | Lu, Wei | en_US |
dc.contributor.committeemember | Kurdak, Cagliyan | en_US |
dc.contributor.committeemember | Guo, L. Jay | en_US |
dc.contributor.committeemember | Zhong, Zhaohui | en_US |
dc.subject.hlbsecondlevel | Electrical Engineering | en_US |
dc.subject.hlbtoplevel | Engineering | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/93932/1/fungw_1.pdf | |
dc.owningcollname | Dissertations and Theses (Ph.D. and Master's) |
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