Flexible Digital-Intensive Wireless Receivers in Nanometer CMOS.

Abstract

Wireless receivers designed in nanometer CMOS processes should take advantage of the strengths of more fundamentally digital topologies and intelligent digital control of analog circuitry. As congestion in the radio spectrum increases, receivers would also benefit from low-power, intelligent filters for interference rejection. Such filters would enable wireless devices on a limited power budget to efficiently share limited spectral resources. Analog discrete-time (DT) filters together with digital control show promise because the capacitors and switches that these filters consist of benefit from device scaling and because easily configurable digital sampling clocks determine their frequency responses.

This work introduces wireless receivers in 65nm CMOS that demonstrate the capabilities of analog DT filters coupled with intelligent digital control. The first receiver replaces conventional filtering stages with a SAR ADC that embeds a highly-integrated DT FIR/IIR filter with programmable FIR tap length and coefficients. Interleaving of the SAR and DT filter sampling processes in this ADC maximizes the conversion rate and facilitates IIR filtering. The prototype receiver supports several standards and bands and exceeds the sensitivity and jammer resistance requirements of both the 915MHz and 2450MHz bands of IEEE 802.15.4, while consuming 4.0mW and 5.5mW, respectively. The second receiver introduces intelligent spectrum-adaptive (SA) filtering. The SA filter performs spectrum-sensing in an auxiliary signal path to detect interferers over a 55MHz range, and then selects the optimal filtering mode of a reconfigurable DT notch filter in the receiver’s main signal path to suppress the strongest detected interferer. The auxiliary spectrum-sensing path isolates the power of interferers using a DT spectrum-analysis bandpass filter and calculates the power contained in the filter’s output using simple DSP. A calibrated on-chip ring-oscillator drives the sampling clocks of the spectrum-analysis filter and enables accurate definition and tuning of the center frequency of its passband. In IEEE 802.15.4 2450MHz packet tests with SA filtering enabled, this receiver achieves ≥+55dB rejection of +25 to +65MHz FM interferers.