Multiobjective Placement Optimization for High-performance Nanoscale Integrated Circuits.

Abstract

With aggressive scaling of semiconductor manufacturing technology in recent decades, the complexity of integrated circuits has increased rapidly leading to multi-million gate chips that require over ten metal routing layers. At current and future technology nodes, semiconductor devices are connected by narrower and more resistive wires, shifting the performance bottleneck from gate delay to interconnect delay. These trends confound modern design technologies for timing closure and require major improvements in physical design automation to maintain the current pace of innovation in chip architecture.

Modern VLSI design flows require considerable effort and time in physical layout, where transistor locations affect nearly all downstream optimizations during timing closure. However, despite impressive improvements developed in academia and industry during the last decade, state-of-the-art algorithms for placement leave room for improvement both in quality and speed. Additionally, mainstream wirelength-driven placement algorithms are not geared for optimizing various objectives that are required by advanced VLSI processes and design styles.

Our research addresses new challenges in physical optimization by (i) identifying the necessary new objectives, constraints and concerns imposed by contemporary and future semiconductor technologies,(ii) integrating these objectives with the existing objectives and tools, and (iii) developing new computational techniques to enhance scalability and robustness. We present new algorithms and methodologies for placement optimization subject to various constraints. In particular, we develop a standalone wirelength-driven global placement algorithm to significantly improve quality of standard-cell locations and decrease runtime. This algorithmic framework was recently adopted in the industry and has been extended by several university groups to support multiobjective optimization. In addition, our research shows how to integrate routability analysis within placement optimization, which is becoming increasingly important at upcoming semiconductor technology nodes. Experimental results indicate that the produced placements are significantly easier to route. We further enhance wirelength-driven placement using a multilevel framework and novel combinatorial optimization techniques. To broaden the scope of placement optimization, we study the theoretical aspects of our placement algorithms,and develop a variety of extensions: to different interconnect models, macro placement, and timing-driven placement. Another such extension is a placement framework that significantly improves the handling of datapath designs.