Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits.

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dc.contributor.author Fick, David A. en_US
dc.date.accessioned 2013-02-04T18:05:21Z
dc.date.available NO_RESTRICTION en_US
dc.date.available 2013-02-04T18:05:21Z
dc.date.issued 2012 en_US
dc.date.submitted 2012 en_US
dc.identifier.uri http://hdl.handle.net/2027.42/96066
dc.description.abstract Historically, consumer computing products have moved to increasingly smaller form factors, from the personal computer, to the laptop, and now to devices such as smart phones and tablets. These products have a high amount of visibility, but in the background are datacenters solving problems beyond what can be solved by consumer devices. One of the first computers, ENIAC, was a massive machine that weighed 30 tons and occupied a full room to calculate artillery firing tables. Now it is possible to build a much more powerful system in a cubic millimeter form factor, but we still build warehouse-size systems, such as the "K computer", to solve complex problems like global weather simulation. Although advances in computing technology have greatly improved system capabilities and form factors, they have introduced problems in heat dissipation, reliability, and yield. Large scale systems are greatly affected by this, where their power usage is measured in megawatts, their reliability goal is running a mere 30 hours without system failure, and their processor count numbers in the hundreds of thousands. This thesis addresses these issues on four fronts. First, 3D-stacking technology coupled with near-threshold computing (NTC) is used to address heat dissipation. A 3D-stacked NTC system, Centip3De, is presented as a demonstration of this strategy, with a 75x decrease in processor power and a 5.1x improvement in energy efficiency. Next, system yield is addressed using a demonstrated in-situ performance monitoring technique, Safety Razor, which uses a novel time-to-digital converter with sub-picosecond calibration accuracy. Third, interconnect and system reliability is addressed with a failure tolerant interconnect fabric, Vicis, which disables faulty components to maintain reliability, tolerating fault rates of over 1 in 2,000 gates. Finally, stochastic computing is proposed as an error-tolerant form of computation for advanced VLSI processes. An example application of an image sensor array with built-in edge detection is investigated, with a power savings improvement of over 50% compared to a conventional approach. en_US
dc.language.iso en_US en_US
dc.subject VLSI en_US
dc.subject Integrated Circuits en_US
dc.subject Network-on-Chip en_US
dc.subject 3DIC en_US
dc.subject Near-threshold Computing en_US
dc.subject Manycore en_US
dc.title Power, Interconnect, and Reliability Techniques for Large Scale Integrated Circuits. en_US
dc.description.thesisdegreename PHD en_US
dc.description.thesisdegreediscipline Computer Science & Engineering en_US
dc.description.thesisdegreegrantor University of Michigan, Horace H. Rackham School of Graduate Studies en_US
dc.contributor.committeemember Sylvester, Dennis Michael en_US
dc.contributor.committeemember Blaauw, David T. en_US
dc.contributor.committeemember Cutler, James W. en_US
dc.contributor.committeemember Wenisch, Thomas F. en_US
dc.contributor.committeemember Mudge, Trevor N. en_US
dc.subject.hlbsecondlevel Computer Science en_US
dc.subject.hlbsecondlevel Electrical Engineering en_US
dc.subject.hlbtoplevel Engineering en_US
dc.description.bitstreamurl http://deepblue.lib.umich.edu/bitstream/2027.42/96066/1/dfick_1.pdf
dc.owningcollname Dissertations and Theses (Ph.D. and Master's)
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