Computational Investigations of Fundamental Plasma Processes in Semiconductor Industrial Applications
Qu, Chenhui
2020
Abstract
The continuous downsizing of the critical dimensions (CDs) of semiconductor devices poses challenges to plasma-involved semiconductor fabrication processes. As the CD decreases to sub-ten nanometers (e.g., 6 nm-width fin field-effect transistor [FinFET]), control of plasma properties to provide atomic scale precision becomes necessary. Meanwhile, to ensure high yield, semiconductor fabrication is often deployed on a large scale, on 300 mm wafers. Therefore, it is essential to have a uniform plasma distribution across the reactor for consistent yields. In this thesis, reactor and feature scale modeling was performed. The research work involves developing computational modules and applying acceleration mechanisms in two simulation platforms: the Hybrid Plasma Equipment Model (HPEM), for reactor scale modeling, and the Monte Carlo Feature Profile Model (MCFPM), for feature scale simulations. Frequency tuning and impedance matching with an impedance matching network (IMN) were implemented in the HPEM to study the electrical dynamics during pulsed-plasma operation. Surface reaction mechanisms of SiO2 plasma-enhanced atomic layer deposition (PE-ALD) using bis-tertiary-butyl-amino-silane (BTBAS) as the precursor were developed. In an inductively coupled plasma (ICP) reactor, the power deposition into the plasma is always less than the output from the power source. The power that is not directed into the plasma is lost in the transmission line, reflected at the coil-plasma interface due to the impedance mismatch, or dissipated by the materials in the plasma reactor. The power reflection is minimized by implementing an IMN between the power source and the coil. By tuning the circuit components used in the IMN, the impedance of the pre-plasma circuit (including coils, IMNs, and power source) is brought close to the impedance of the plasma, thus reducing the power reflection. However, in practice, the components in an IMN have fixed values because tuning the IMN is a mechanical process that takes several miliseconds to even seconds. Frequency tuning is another mechanism for impedance matching, which takes advantage of the high tuning rate with solid state electronics. This technique can be used with an IMN if the plasma has a rapidly changing impedance (e.g., pulsed plasma). The function of analytically calculating the circuit components in IMN to minimize power reflection in an ICP reactor was implemented in the HPEM. An algorithm of frequency tuning in an ICP was also added to enable impedance matching by adjusting RF frequency when the IMN is fixed. SiO2 films are widely used in semiconductor devices, and PE-ALD is a preferred method for deposition when a low process temperature is needed. The PE-ALD of SiO2 has two major steps: precursor dosing and plasma exposure. During precursor dosing, a silicon precursor such as BTBAS is used to treat the target surface and forms a monolayer of Si-H compounds. Subsequently, in the plasma exposure step, the target surface is treated with an oxygen plasma and is oxidized. The reaction is self-limiting for both steps, and a monolayer of SiO2 is deposited in one cycle. However, in experiments, the growth-per-cycle (GPC) is often less than one monolayer, which partly is caused by steric hindrance. Incomplete reactions during precursor dosing leave alkyl ligand remains on the target surface, which block neighboring sites, and slows the deposition. The impacts of the operating conditions and steric hindrance on SiO2 films during PE-ALD were studied.Subjects
low temperature plasma semiconductor fabrication
Types
Thesis
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